A signal line is a conductor used to transmit electrical signals between various devices in an electronic system or between devices located in two separate electronic systems. Output driver circuits contained on each device are used to buffer signals originating from the device so that they may be driven onto the signal lines.
There are well known single-ended output driver circuits (e.g., TTL drivers) that are simple to use. However, most of these previously disclosed driver circuits are not suitable for high speed signals due to their low maximum operating frequency and high noise. For example, the maximum operating frequency of a single-ended CMOS driver circuit IDT74FCT3807D/E, which is available from Integrated Device Technology, Inc. of Santa Clara, Calif., is 166 Mhz. As another example, the maximum operating frequency of a single-ended 1 input to 5 outputs CMOS driver circuit PI49FCT3802, which is available from Pericom Semiconductor Corporation of San Jose, Calif., is 156 Mhz. Other manufacturers such as On Semiconductors, Philips Semiconductors, Integrated Circuit Systems, Inc., also offer similar products that have similar maximum operating frequencies.
For driving high speed signals, differential drivers are often used. A typical differential driver 10 is schematically illustrated in FIG. 1. The differential driver 10 includes data inputs 12a-12b for inputting a differential data signal, and data outputs 14a-14b for providing the differential signal to a differential receiver 16 via signal lines. The arrangement of FIG. 1 is well known to have high operating frequency. However, differential interface designs have disadvantages as well. First, every differential signal requires two or more signal lines. Therefore, a differential I/O interface will require at least twice the number of pins than a single-ended I/O interface, resulting in a larger chip. Furthermore, high speed systems generally require careful matching of the electrical length of the signal lines such that synchronous signals may be received with a common clock and a common phase. This design requirement is sometimes known as “length matching” or “delay matching.” A wide differential interface will require a large number of signal lines, necessarily complicating the length matching effort and increasing the cost of manufacture. In some instances, length matching many signal lines may be impossible on tightly packed circuit boards. Thus, at least in some electronic systems, it is not desirable to use differential interfaces.
Accordingly, a single-ended output interface design that communicates single-ended signals at a performance level that is comparable to that of a differential interface may be desirable.